The present invention relates to a method and/or architecture for implementing multiplexers generally and, more particularly to a method and/or architecture for implementing programmable tri-state circuits that may be used as multiplexer elements.
A number of conventional programmable approaches may be used to implement multiplexers. Such conventional approaches typically implement a pass gate, an inverter driving the pass gate or an enabled inverter.
Referring to FIG. 1, a diagram of a circuit 10 implementing a conventional multiplexer bit with a simple pass gate is shown. The circuit 10 comprises a multiplexer bit circuit 12, a device 14 and an inverter 16. The circuit 12 is sized for speed (i.e., the input loading depends on size of device, as the size increases the input loading increases). The circuit 12 loads the input IN when the bit 12 is selected via the signal SEL. The circuit 10 also implements a level restore circuit, since a full HIGH cannot be passed through the n-channel device within the multiplexer bit 12. Level restore circuits are connected to the output of a multiplexer, where a multiplexer is implemented as multiple outputs of the bits 12 connected together. Therefore, a driver (not shown) configured to drive the input signal IN needs to over-power multiple level restore circuits, when implemented in a multiplexer design.
Referring to FIG. 2, a diagram of circuit 30 implementing another conventional multiplexer bit circuit 32 with a pass gate and an inverter is shown. The circuit 30 comprises a multiplexer bit circuit 32, a device 34 and an inverter 36. An inverter 38 within the multiplexer bit 32 isolates the internal nodes of the circuit 30 from the input IN. However, the circuit 32 consumes current independent of the multiplexer bit selection signal SEL due to an output of the inverter 38 switching when the input IN switches. The circuit 30 also implements a level restore circuit, since a full HIGH level cannot be passed through the n-channel device within the multiplexer bit 32. Level restore circuits can be connected to the output of a multiplexer, where a multiplexer is implemented as a number of the circuits 32 having outputs connected together.
Referring to FIG. 3a, a diagram of a circuit 50 implementing a conventional multiplexer bit with an enabled inverter is shown. While the circuit 50 does not implement a level restore circuit, the circuit 50 has a number of disadvantages. For example, the circuit 50 has a large gate load on the input IN. The gate load is large since the series transistors are sized to have an equivalent drive strength as a single transistor.
Referring to FIG. 3b, a diagram of a circuit 52 implementing another conventional multiplexer bit with an enabled inverter is shown. The circuit 52, when implemented in large multiplexer configurations, has an excess amount of capacitance that appears in parallel with an input of an inverting amplifier stage between the output and the input signal IN caused by the gate overlap capacitance. The circuit 52 does not implement a level restore circuit, but has a number of disadvantages. For example, the output of a multiplexer can switch and couple to the input of an unselected bit, which causes the input to glitch or delay the input transition time. Also, the input can couple to the output and cause the output to glitch or delay the output transition time.
Conventional approaches have one or more of the following disadvantages: (i) adding loading to input lines; (ii) adding increased loading if other multiplexer bits are already connected to the input lines; (iii) switching currents that are consumed by an unconfigured bit; and (iv) lack of isolation between the output node and the input node.
The present invention concerns an apparatus comprising an input section and an output section. The input section may be configured to generate a first control signal and a second control signal in response to an input signal and a select signal. The output section may be configured to generate an output signal in response to the first and second control signals. The output signal may be (i) related to the input signal when in a first mode and (ii) disabled when in a second mode.
The objects, features and advantages of the present invention include providing a method and/or architecture for implementing a programmable tri-state circuit that may be used for constructing multiplexers that may (i) allow isolation of the output load from the input, (ii) prevent switching when the circuit is not configured (or enabled), (iii) provide rail to rail output levels, (iv) be implemented with only a small loading penalty, (v) connect an input to multiple multiplexer bits to enhance the overall routability of a switching matrix, and/or (vi) implement multiplexers that, when implemented in groups, provide consistent speed (or delay) without suffering performance penalties as the number of selected multiplexer bits connected to an input increases.